Average Rectified Peak Surge Average
Current Current,Ifsm Forward
PIV Forward(Reverse) 1sec.@25C Voltage, Vf
Device type Material (Volts) Io(A)(Ir(A)) (A) (Volts)
1N34 Signal Germanium 60 8.5m(15.0u) - 1.0
1N34A Signal Germanium 60 5.0m(30.0u) - 1.0
1N67A Signal Germanium 100 4.0m( 5.0u) - 1.0
1N191 Signal Germanium 90 5.0m - 1.0
1N270 Signal Germanium 80 0.2 (100u) - 1.0
1N914 Fast Silicon(Si) 75 10.0m(25.0n) 0.5 1.0
Switch
1N1184 (RFR) Si 100 35.0m(10m ) - 1.7
Rectifier
Fast
Recovery
1N2071 RFR Si 600 0.75m(10.0u) - 0.6
1N3666 Signal Germanium 80 0.2m(25.0u) - 1.0
1N4001 RFR Si 50 1.0 (0.03m) - 1.1
1N4002 RFR Si 100 1.0 (0.03m) - 1.1
1N4003 RFR Si 200 1.0 (0.03m) - 1.1
1N4004 RFR Si 400 1.0 (0.03m) - 1.1
1N4005 RFR Si 600 1.0 (0.03m) - 1.1
1N4006 RFR Si 800 1.0 (0.03m) - 1.1
1N4007 RFR Si 1000 1.0 (0.03m) - 1.1
Average Rectified Peak Surge Average
Current Current,Ifsm Forward
PIV Forward(Reverse) 1sec.@25C Voltage, Vf
Device type Material (Volts) Io(A)(Ir(A)) (A) (Volts)
1N4148 Signal Si 75 10.0m(25.0n) - 1.0
1N4149 Signal Si 75 10.0m(25.0n) - 1.0
1N914 Fast Si 40 20.0m(0.05u) - 0.8
Switch
1N4445 Signal Si 100 0.1(50.0n) - 1.0
1N5400 RFR Si 50 3.0 200 -
1N5401 RFR Si 100 3.0 200 -
1N5402 RFR Si 200 3.0 200 -
1N5403 RFR Si 300 3.0 200 -
1N5404 RFR Si 400 3.0 200 -
1N5405 RFR Si 500 3.0 200 -
1N5406 RFR Si 600 3.0 200 -
1N5767 Signal Si - 0.1(1.0u) - 1.0
EGC5863 RFR Si 600 6 150 0.9
source from qsl
Selasa, 30 September 2008
SEMICONDUCTOR DIODA
74AC240 OCTAL BUS BUFFER WITH 3 STATE OUTPUTS (INVERTED)
April 1997
n HIGH SPEED: tPD = 4 ns (TYP.) atVCC = 5V
n LOWPOWER DISSIPATION:
ICC = 8 mA (MAX.) at TA =25 oC
n HIGH NOISE IMMUNITY:
VNIH =VNIL = 28%VCC (MIN.)
n 50W TRANSMISSIONLINE DRIVING
CAPABILITY
n SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL =24mA (MIN)
n BALANCED PROPAGATIONDELAYS:
tPLH @ tPHL
n OPERATINGVOLTAGERANGE:
VCC (OPR) = 2V to 6V
n PIN AND FUNCTION COMPATIBLEWITH
74 SERIES 240
n IMPROVEDLATCH-UP IMMUNITY
DESCRIPTION
The AC240 is an advanced CMOS OCTAL BUS
BUFFER (3-STATE) fabricated with sub-micron
silicon gate and double-layer metal wiring C2MOS
technology. It is ideal for low power applications
mantaining high speed operation similar to
equivalent Bipolar Schottky TTL.
G control output governs four BUS BUFFERs.
This device is designed to be used with 3 state
memory address drivers, etc.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGICSYMBOLS
ORDER CODES :
74AC240B 74AC240M
M
(Micro Package)
B
(Plastic Package)
1/8
INPUT AND OUTPUT EQUIVALENTCIRCUIT
TRUTH TABLE
INPUT OUTPUT
G An Yn
L L H
L H L
H X Z
X:”H” or ”L”
Z:High impedance
PIN DESCRIPTION
PIN No SYMBOL NAME AND FUNCTION
1 1G Output Enable Input
2, 4, 6, 8 1A1 to 1A4 Data Inputs
9, 7, 5, 3 2Y1 to 2Y4 Data Outputs
11, 13, 15, 17 2A1 to 2A4 Data Inputs
18, 16, 14, 12 1Y1 to 1Y4 Data Outputs
19 2G Output Enabel Input
10 GND Ground (0V)
20 VCC Positive Supply Voltage
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
VCC Supply Voltage -0.5 to +7 V
VI DC Input Voltage -0.5 toVCC +0.5 V
VO DC Output Voltage -0.5 toVCC +0.5 V
IIK DC Input Diode Current ± 20 mA
IOK DC Output Diode Current ± 20 mA
IO DC Output Current ± 50 mA
ICC or IGND DC VCC or Ground Current ± 400 mA
Tstg Storage Temperature -65 to +150 oC
TL Lead Temperature (10 sec) 300 oC
AbsoluteMaximumRatings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Value Unit
VCC Supply Voltage 2 to 6 V
VI Input Voltage 0 toVCC V
VO Output Voltage 0 toVCC V
Top Operating Temperature: -40 to +85 oC
dt/dv Input Rise and Fall Time VCC = 3.0, 4.5 or 5.5 V(note 1) 8 ns/V
1) VIN from30% to 70%of VCC
74AC240
2/8
DC SPECIFICATIONS
Symbol Parameter Test Conditions Value Unit
VCC
(V)
TA = 25 oC -40to85o
C
Min. Typ. Max. Min. Max.
VIH High Level Input Voltage 3.0 VO =0.1Vor
VCC -0.1V
2.1 1.5 2.1
4.5 3.15 2.25 3.15 V
5.5 3.85 2.75 3.85
VIL Low Level Input Voltage 3.0 VO =0.1Vor
VCC -0.1V
1.5 0.9 0.9
4.5 2.25 1.35 1.35 V
5.5 2.75 1.65 1.65
VOH High Level Output
Voltage
3.0
VI
(*)=
VIH or
VIL
IO=-50 mA 2.9 2.99 2.9
V
4.5 IO=-50 mA 4.4 4.49 4.4
5.5 IO=-50 mA 5.4 5.49 5.4
3.0 IO=-12 mA 2.56 2.46
4.5 IO=-24 mA 3.86 3.76
5.5 IO=-24 mA 4.86 4.76
VOL Low Level Output
Voltage
3.0
VI
(*)=
VIH or
VIL
IO=50 mA 0.002 0.1 0.1
V
4.5 IO=50 mA 0.001 0.1 0.1
5.5 IO=50mA 0.001 0.1 0.1
3.0 IO=12mA 0.36 0.44
4.5 IO=24mA 0.36 0.44
5.5 IO=24mA 0.36 0.44
II Input Leakage Current 5.5 VI =VCC orGND ±0.1 ±1 mA
IOZ 3 State Output Leakage
Current
5.5 VI =VIH or VIL
VO =VCC orGND
±0.5 ±5 mA
ICC Quiescent Supply
Current
5.5 VI =VCC orGND 8 80 mA
IOLD Dynamic Output Current
(note 1, 2)
5.5 VOLD =1.65Vmax 75 mA
IOHD VOHD =3.85Vmin -75 mA
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as lowas 50W.
(*)All outputs loaded.
74AC240
3/8
CAPACITIVE CHARACTERISTICS
Symbol Parameter Test Conditions Value Unit
VCC
(V)
TA = 25 oC -40 to 85 oC
Min. Typ. Max. Min. Max.
CIN Input Capacitance 5.0 4 pF
COUT Output Capacitance 5.0 8 pF
CPD Power Dissipation
Capacitance (note 1)
5.0 21 pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to
Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/n (per circuit)
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 W, Input tr = tf =3 ns)
Symbol Parameter Test Condition Value Unit
VCC
(V)
TA = 25 oC -40to85o
C
Min. Typ. Max. Min. Max.
tPLH
tPHL
Propagation Delay Time 3.3(*) 1.5 5 8 1.5 9
ns
5.0(**) 1.5 4 6.5 1.5 7
tPZL
tPZH
Output Enable Time 3.3(*) 1.5 7 10.5 1.5 11.5
ns
5.0(**) 1.5 5 8 1.5 8.5
tPLZ
tPHZ
Output Disable Time 3.3(*) 1.5 7 10.5 1.5 11.5
ns
5.0(**) 1.5 6 9 1.5 9.5
(*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is5V ± 0.5V
TEST CIRCUIT
TEST SWITCH
tPLH, tPHL Open
tPZL, tPLZ 2VCC
tPZH, tPHZ Open
CL = 50 pF or equivalent (includes jig and probe capacitance)
RL =R1 = 500W or equivalent
RT =ZOUT of pulse generator (typically 50W)
74AC240
4/8
WAVEFORM 1: PROPAGATION DELAYS (f=1MHz;50% duty cycle)
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
74AC240
5/8
DIM.
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
a1 0.254 0.010
B 1.39 1.65 0.055 0.065
b 0.45 0.018
b1 0.25 0.010
D 25.4 1.000
E 8.5 0.335
e 2.54 0.100
e3 22.86 0.900
F 7.1 0.280
I 3.93 0.155
L 3.3 0.130
Z 1.34 0.053
P001J
Plastic DIP20 (0.25) MECHANICAL DATA
74AC240
6/8
SO20 MECHANICAL DATA
DIM.
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 2.65 0.104
a1 0.10 0.20 0.004 0.007
a2 2.45 0.096
b 0.35 0.49 0.013 0.019
b1 0.23 0.32 0.009 0.012
C 0.50 0.020
c1 45° (typ.)
D 12.60 13.00 0.496 0.512
E 10.00 10.65 0.393 0.419
e 1.27 0.050
e3 11.43 0.450
F 7.40 7.60 0.291 0.299
L 0.50 1.27 0.19 0.050
M 0.75 0.029
S 8° (max.)
P013L
74AC240
7/8
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise underany patent or patent rights ofSGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSONMicroelectronics products are not authorized for use as criticalcomponents in life supportdevices or systems without expresswritten approval of SGS-THOMSON Microelectonics.
74AC240
8/8
Characteristics for many 74X logic families
I got mail from several people expressing interest in this table of device characteristics for many 74X logic families. I have tried to include all of the common (and obsolete) families. I have included a basic logic gate (74x00), a tri-state buffer (74x244), and a flip-flop (74x374). I have not included a latch, just to get a religious debate about the difference between a latch and flip-flop going :) To reduce confusion, here are the meanings of the mnemonics I have used:
tPLH - prop delay from low to high
tPHL - prop delay from high to low
VOH - logic level 1 output voltage
VOL - logic level 0 output voltage
VIH - logic level 1 input voltage
VIL - logic level 0 input voltage
IOH, IOL, IIH, IIL - similarly
tPZH - prop delay from high impedance to high
tPZL - prop delay from high impedance to low
tPHZ, tPLZ - similarly
f - toggle frequency
Note that prop delays for the x374s are clock to Q times. I use the output and input voltages to calculate noise margins and output and input currents for DC loading calculations. I hope that ya'll find this table of use. Of course, forward any errors to me, but keep differences at the right of the decimal point to yourselves, I'm a digital guy and such minor errors don't affect me :) The vendor chosen for each family is given next to each device. The vendor was chosen by which data book I happened to pick up first. Enjoy. Thanks to Jarrod Johnson for typing it all in.
tPLH(max) [ns] tPHL(max) [ns] VOH(min) [V] VOL(max) [V] VIH(min) [V] VIL(max) [V] IOH(max) [mA] IOL(max) [mA] IIH(max) [uA] IIL(max) [mA]
7400 (TI) 22 15 2.4 0.4 2 0.8 -0.4 16 40 -1.6
74S00 (TI) 4.5 5 2.7 0.5 2 0.8 -1 20 50 -2
74LS00 (TI) 15 15 2.7 0.4 2 0.8 -0.4 8 20 -0.4
74ALS00 * (National) 11 8 3 0.4 2 0.8 -0.4 8 20 -0.1
74F00 (Signetics) 5 4.3 2.5 0.5 2 0.8 -1 20 20 -0.6
74HC00 ** (TI) 23 23 3.84 0.33 3.15 0.9 -4 4
74AC00 ** (TI) 8 6.5 4.4 0.1 3.15 1.35 -75 75
74ACT00 ** (TI) 9 7 4.4 0.1 2 0.8 -75 75
tPLH(max) tPHL(max) tPZH(max) tPZL(max) tPHZ(max) tPLZ(max) VOH(min) VOL(max) VIH(min) VIL(max) IOH(max) IOL(max) IIH(max) IIL(max)
ns ns ns ns ns ns V V V V mA mA uA mA
74S244 (TI) 9 9 12 15 9 15 2.4 0.55 2 0.8 -15 64 50 -2
74LS244 (TI) 18 18 23 30 25 20 2.4 0.4 2 0.8 -15 24 20 -0.2
74ALS244 * (National) 10 10 20 20 10 13 3 0.4 2 0.8 -15 24 20 -0.1
74F244 (Signetics) 5.2 5.2 6.7 8 6 5.5 2.5 0.55 2 0.8 -15 64 20 -1
74HCT244 (TI) 35 35 44 44 44 44 3.84 0.33 2 0.8 -6 6
74HC244 ** (TI) 29 29 38 38 38 38 3.84 0.33 3.15 0.9 -6 6
74AC244 (TI) 7 7 7 8 9 9 3.76 0.44 3.15 1.35 -24 24
74ACT244 (TI) 9 9 8.5 9.5 9.5 10 3.76 0.44 2 0.8 -24 24
74BCT244 (TI) 4.4 6 7.8 8.1 6.7 7.6 2 0.55 2 0.8 -15 64 20 -1
74ABT244 (TI) 4.6 4.6 5.1 6.1 6.6 5.7 2 0.55 2 0.8 -24 64
74FCT244T (Quality) 3.8 3.8 5.6 5.6 5.2 5.2 2.4 0.55 2 0.8 -15 64 5 -0.005
f(max) tPLH(max) tPHL(max) tPZH(max) tPZL(max) tPHZ(max) tPLZ(max) VOH(min) VOL(max) VIH(min) VIL(max) IOH(max) IOL(max) IIH(max) IIL(max)
MHz ns ns ns ns ns ns V V V V mA mA uA mA
74S374 (TI) 100 15 17 15 18 9 12 2.4 0.5 2 0.8 -6.5 20 50 -0.25
74LS374 (TI) 50 28 28 26 28 28 20 2.4 0.5 2 0.8 -2.6 24 20 -0.4
74ALS374 ** (National) 35 12 16 17 18 10 18 3 0.5 2 0.8 -2.6 24 20 -0.2
74F374 (Signetics) 150 7.5 7.5 11 7.5 6 5.5 2.4 0.5 2 0.8 -3 24 20 -0.6
74HCT374 (TI) 25 45 45 38 38 38 38 3.84 0.33 2 0.8 -6 6
74HC374 ** (TI) 24 45 45 38 38 38 38 3.84 0.33 3.15 0.9 -6 6
74AC374 (TI) 155 9.5 9 8.5 8.5 11 8.5 3.76 0.44 3.15 1.35 -24 24
74ACT374 (TI) 160 10 9.5 9.5 9 11.5 8.5 3.76 0.44 2 0.8 -24 24
74BCT374 (TI) 70 9.1 8.8 10.1 10.6 6.3 6.3 2 0.55 2 0.8 -15 64 20 -0.6
74ABT374 (TI) 150 6.2 7.1 5.2 6.7 6.5 6.5 2 0.55 2 0.8 -24 64
74FCT374T (Quality) 250 4.5 4.5 5.5 5.5 5 5 2.4 0.5 2 0.8 -15 48 5 -0.005
* for VOH, assume VCC=5 V
** for VOH, assume VCC=4.5 V
source from qsl
